1. "ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs," Chenhui Deng, Zhongzhi Yu, Guan-Ting Liu, Nathaniel Pinckney, Haoxing Ren
2. "Agentic Multi-Turn Reinforcement Learning for Boosting Verilog Code Generation," Qiufeng Li, Weidong Cao
3. "EDAForge: A Multi-Agent Orchestration Framework for Autonomous Analog Circuit Synthesis," Weimin Fu, Zining Wang, Jian Gao, Xuan Zhang, Xiaolong Guo
4. "MACO: A Multi-Agent Framework for LLM-Driven Hardware/Software Co-Design," Zesong Jiang, Sriram Krishnamoorthy, Cheng Tan, Jeff Zhang
5. "ASPEN: LLM-Guided E-Graph Rewriting for RTL Datapath Optimization," Niansong Zhang, Chenhui Deng, Johannes Maximilian Kuehn, Chia-Tung Ho, Cunxi Yu, Zhiru Zhang, Haoxing Ren
6. "LLM4Cov: Execution-Aware Agent Learning for High-coverage Testbench Generation," Hejia Zhang, Zhongming Yu, Chia-Tung Ho, Haoxing Ren, Brucek Khailany, Jishen Zhao
7. "VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space," Yu-Tung Liu, Cunxi Yu
8. "ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design," zhongkai yu, Chenyang Zhou, Yichen Lin, Hejia Zhang, Haotian Ye, Junxia Cui, Zaifeng Pan, Jishen Zhao, Yufei Ding
9. "GACO: Graph-Augmented Code Optimization for Automated HLS Design," Haocheng Xu, Phyo Pyae Moe Aung, Adam Han Wu, Sitao Huang
10. "Influential Data Selection for LLM-based RTL Generation," Zhan Song, Cunxi Yu
11. "FVRuleLearner: An SVA Generation Agent with Rule Learning via Operator-Level Reasoning Trees," Lily Jiaxin Wan, Chia-Tung Ho, Yunsheng Bai, Cunxi Yu, Deming Chen, Haoxing Ren
12. "RAG-Enhanced Kernel-Based Heuristic Synthesis (RKHS): A Structured Methodology Using Large Language Models for Hardware Design," Shiva Ahir, Alex Doboli
13. "Can an Actor-Critic LLM Framework Improve Analog Design Optimization?," Sounak Dutta, Sushil Panda, Fin Amin, Jonathan Rabe, Yuejiang Wen, Paul Franzon
14. "AnuRAG: Empowering Analog Designers with White-Box RAG for Rapid Design Space Exploration," Vikas Kumar, Boris Murmann
15. "NoTB: Oracle-Free Triage of LLM-Generated RTL via Cross-Variant Formal Equivalence," Elisavet Lydia Alvanaki, Je Yang, Luca Carloni
16. "VerifEval: Comprehensive Evaluation of AI-Generated Hardware Verification with Simulation, Coverage, and Formal Checks," Tamzid Razzaque, Sulaiman Islam, Rohil Khare, Nabil Abdelaziz Ferhat Taleb
17. "LACE: A Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension," Pingzhi Fu, Jiayin Qin, Fuqi Zhang, Yu Cao, Caiwen Ding, Yang Katie Zhao
18. "HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization," Souradip Poddar, Chia-Tung Ho, Ziming Wei, Weidong Cao, Haoxing Ren, David Z. Pan
19. "Stepping Stones Towards Agentic HLS Design," Stefan Abi-Karam, Callie Hao
20. "Exploring AI-Driven approaches for scalable ASIC design and implementation," Vikas Gupta
21. "Iceberg++: Scaling High-Quality Synthetic Data for HLS," Yang Zou, Zijian Ding, Yizhou Sun, Jason Cong
22. "PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification," Yujie Zhao, Zhijing Wu, Boqin Yuan, Zhongming Yu, Hejia Zhang, Wentao Ni, Chia-Tung Ho, Haoxing Ren, Jishen Zhao
23. "ARLArena: A Unified Framework for Stable Agentic Reinforcement Learning," Xiaoxuan Wang, Han Zhang, Haixin Wang, Yidan Shi, Ruoyan Li, Kaiqiao Han, Chenyi Tong, Haoran Deng, Renliang Sun, Alexander Taylor, Yanqiao Zhu, Jason Cong, Yizhou Sun, Wei Wang