Chia-Tung (Mark) Ho (Nvidia)
Learning Agentic AI for Hardware Design Automation: From Hand-Crafted Workflows to Trainable, Self-Improving Agents
Abstract
Hand crafted agentic AI workflows for hardware design automation are difficult to evolve, hard to adapt across heterogeneous EDA tool interfaces, and challenging to scale across workloads spanning RTL, verification, physical design, and manufacturing. Extending an agent from one flow to the next often resembles re-engineering rather than learning, limiting generalizability and maintainability.
This talk reframes agentic hardware design automation as a trainable, self-improving system. We present three complementary studies that demonstrate learning at different levels of the design automation stack: self-improving workflows that iteratively refine agent execution through experience and self-evolution, operator-level rule learning for formal verification that extracts reasoning traces from learned operator-level reasoning trees, and autonomous log ingestion using question trees and gradient boosting to extract knowledge from diverse log formats. These methods demonstrate self-learning approaches where agents improve from experience, transfer across workflows, and reduce dependence on manual prompt engineering, pointing toward continuously improving hardware design automation systems.
Bio
Chia-Tung has several years of industrial EDA experience under his belt. Before coming to US, he worked for IDM and EDA companies in Taiwan, developing in-house design for manufacturing (DFM) flow at Macronix, and fastSPICE at Mentor Graphics and Synopsys. During his PhD study, he worked with the Design Technology Co-Optimization (DTCO) team in Synopsys as a technical intern from 2019 to 2021, also as an AI resident in X, the Google moonshot factory. In Nvidia, he works as senior research scientist on ML/AI for VLSI, Agentic AI for chip design, custom circuit design, and standard cell layout synthesis.