Vikas Gupta (Samsung)
Exploring AI-Driven Approaches for Scalable ASIC Design and Implementation
Abstract
As ASIC designs continue to grow in complexity at advanced technology nodes, traditional rule-based implementation methodologies are increasingly challenged in terms of scalability, productivity, and debuggability. This work presents ongoing efforts to explore and integrate AI-driven techniques into key stages of the ASIC physical design flow, with the goal of augmenting engineering decision-making and improving overall design efficiency.
We are actively developing an AI-assisted tapeout agent intended to support engineers throughout the implementation cycle, enabling a single designer to effectively manage a larger number of digital blocks. The agent is being trained using historical design data, implementation flows, and tapeout outcomes to provide context-aware guidance during critical phases of the flow.
Another area of active investigation focuses on large digital channels, where thousands of signals must be buffered and routed under tight electrical and physical constraints. We are exploring AI-based methods to analyze signal behavior, switching activity, congestion patterns, and routing rules in order to assist with decisions related to buffer placement, non-default routing rules (NDR), metal layer selection, and signal adjacency.
We are also examining the use of AI for post-silicon debug, particularly for LVCC-related failures. By correlating voltage drop data, static timing analysis, and physical design databases, our approach aims to reduce the effort required to identify potential root causes of cell failures across operating conditions.
Finally, we are investigating AI techniques to analyze full-chip timing results and identify systematic timing bottlenecks, with the objective of guiding more effective timing closure strategies. These ongoing efforts represent a step toward more data-driven, adaptive, and scalable ASIC implementation flows.
Bio
Vikas Gupta is a Senior Director at Samsung Semiconductor, where he leads design and implementation teams for advanced SoC technologies. With over 20 years of experience in physical design and more than 35 successful tape-outs, he has worked hands-on up to 4nm nodes. Over the last two years, Vikas has driven multiple initiatives to optimize ASIC implementation flows using AI, improving efficiency and design outcomes. He has previously held leadership roles at Google, SanDisk, Synopsys, and Samsung, contributing to physical design methodology development across the semiconductor industry. Vikas is an alumnus of IIT, Varanasi.