In the past few years, domain-specific accelerators (DSAs), such as Google's Tensor Processing Unit (TPU), have shown to offer significant performance and energy efficiency over general-purpose CPUs. However, DSAs require deep hardware knowledge to achieve high performance. Unfortunately, there are far fewer hardware designers than software developers. Leveraging AI techniques to further automate chip design becomes the key to meeting the need of rapid change in software development, which is also critical for democratizing hardware design and creating next-generation energy-efficient hardware. This workshop aims to bring researchers and practitioners from both machine learning and EDA communities to discuss how AI can address challenges in different stages of hardware design, promoting open benchmark datasets and open discussions to revolutionize chip design.

The workshop will consist of invited talks and panel discussions on a wide variety of methods and problems in this area, including but not limited to:

• Graph Neural Networks for performance, power, and area (PPA) prediction and optimization for all stages of EDA pipeline, including HLS, RTL/logic synthesis, and physical designs;
• LLM-based code analysis for PPA prediction and optimization at all stages of EDA pipeline;
• Multi-modality ML models (e.g., LLM + GNN) for PPA prediction and optimization at all stages of EDA pipeline;
• Domain and task transfer for HLS performance prediction with new kernels and new versions of EDA tools at different stages;
• ML methods to optimize circuit aging and reliability;
• ML for design technology co-optimization (DTCO);
• ML for analog, mixed-signal, and RF IC designs;
• Reinforcement Learning for Design Space Exploration (DSE);
• LLM-based design generation;
• Active learning and importance sampling of design points;
• AI for compiler and code transformation;
• Benchmark datasets.