Call for Posters

Our workshop welcomes posters in the following topics:

Graph Neural Networks for performance, power, and area (PPA) prediction and optimization for all stages of EDA pipeline, including HLS, RTL/logic synthesis, and physical designs;
LLM-based code analysis for PPA prediction and optimization at all stages of EDA pipeline;
Multi-modality ML models (e.g., LLM + GNN) for PPA prediction and optimization at all stages of EDA pipeline;
Domain and task transfer for HLS performance prediction with new kernels and new versions of EDA tools at different stages;
ML methods to optimize circuit aging and reliability;
ML for design technology co-optimization (DTCO);
ML for analog, mixed-signal, and RF IC designs;
Reinforcement Learning for Design Space Exploration (DSE);
LLM-based design generation;
Active learning and importance sampling of design points;
AI for compiler and code transformation;
Benchmark datasets.

Submission Guidelines

Formatting: The submission should be a 3-page pdf file following the NeurIPS 2024 template. This submission should contain title, authors (affiliations and email addresses), a short abstract, background introduction, and a summary of the proposed problem, methods, and main results. References are excluded from the page limit.
Originality: The submission is encouraged to be unpublished or recently accepted work due to the forward-looking nature of the workshop.
Poster presentation: All accepted submissions will be presented as posters on the workshop day.
Submission link: Please submit through this submission link.
Submission deadline: November 4, 2024, 11:59 PM UTC-12 (AoE)
Notification date: November 10, 2024 (or earlier, as soon as we finish reviewing)
Late submission deadline: November 11, 2024, 11:59 PM UTC-12 (AoE) (we will review quickly after it)

Accepted Posters

"Hybrid Graph Representation and Learning Framework for High-Level Synthesis Design Space Exploration," Pouya Taghipour, Eric Granger, Yves Blaquiere (École de Technologie Supérieure). ID: 1
"Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesis," Weikai Li, Ding Wang, Zijian Ding, Atefeh Sohrabizadeh, Zongyue Qin, Jason Cong, Yizhou Sun (University of California - Los Angeles). ID: 2
"CTGAN-Bandit: A Conditional Tabular GAN Model Leveraging Upper Confidence Bound Estimators for Hardware Design Verification," Lorenzo Ferretti, Surya Teja Bandlamudi, Nihar Athreyas, Michael Yan, Vikram Narayan, Samir Mittal (Micron Technology). ID: 3
"AnalogCoder: Analog Circuit Design via Training-Free Code Generation," Yao Lai¹, Sungyoung Lee², Guojin Chen³, Souradip Poddar², Mengkang Hu¹, David Z. Pan², Ping Luo¹ (¹The University of Hong Kong, ²The University of Texas at Austin, ³The Chinese University of Hong Kong). ID: 4
"FloorSet: Benchmark for AI-driven Floorplanning," Uday Mallappa, Hesham Mostafa, Mikhail Galkin, Mariano Phielipp, Somdeb Majumdar (Intel Labs). ID: 5
"Inverse Patterning Technology with Transformer-Based Optimization," Sooyong Lee¹, Guandao Yang², Suyeon Choi², Seongtae Jeong¹, Gordon Wetzstein² (¹Samsung Electronics, ²Stanford University). ID: 6
"Coverage Closure with an Agentic LLM Workflow," Ximin Shan, Rahul Krishnamurthy, Jayanth Raman, Nick Cheng, Vikram Narayan, Samir Mittal (Micron Technology). ID: 7
"AI to Reduce Wasted Time in FPGA Routing," Andrew David Gunter, Steven Wilton (The University of British Columbia). ID: 8
"Deep Learning Enabled Design of RF/mmWave Circuits," Emir Ali Karahan¹, Jonathan Zhou¹, Zheng Liu², Kaushik Sengupta¹ (¹Princeton University, ²Texas Instruments). ID: 9
"Multi-Objective Bayesian Optimization for Efficient HDnn-PIM Software-Hardware Co-Design with Metric Constraints," Chien-Yi Yang¹, Tim Chen¹, Minxuan Zhou², Flavio Ponzina¹, Dongxia Wu¹, Raid Ayoub³, Pietro Mercati³, Mahesh Subedar³, Yian Ma¹, Rose Yu¹, Tajana Rosing¹ (¹University of California - San Diego, ²Illinois Institute of Technology, ³Intel). ID: 10
"NetVGE: Netwise Hardware Trojan Detection at RTL Using Variable Dependency and Knowledge Graph Embedding," Yaroslav Popryho, Debjit Pal, Inna Partin-Vaisband (University of Illinois Chicago). ID: 11
"PromptV: Leveraging LLM-Powered Multi-Agent Prompt Learning for High-Quality Verilog Generation," Zhendong Mi¹, Renming Zheng¹, Haowen Zhong², Yue Sun³, Shaoyi Huang¹ (¹Stevens Institute of Technology, ²University of Washington, ³Lehigh University). ID: 12
"LLM-VeriPPA: Power, Performance, and Area-aware Verilog Code Generation and Refinement with Large Language Models," Kiran Thorat¹, Jiahui Zhao¹, Amit Hasan¹, Yaotian Liu², Xi Xie¹, Hongwu Peng¹, Bin Lei¹, Jeff Zhang², Caiwen Ding³ (¹University of Connecticut, ²Arizona State University, ³University of Minnesota). ID: 13
"Simulator Generation via Large Language Models: A Custom Programming Interface Approach," Jihoon Hong, Hyewon Suh, Yonggan Fu, Yingyan (Celine) Lin (Georgia Institute of Technology). ID: 14
"Balor with Merlin Compiler: Exploiting Diversity of Kernel Representation and Multi-Dataset Learning," Emmet Murphy, Lana Josipovic (ETH Zürich). ID: 15
"VeriDPO: Exploring Alignment for Verilog Designs," Daniel Kiesewalter, Luca Valente, Andrea Bonetti, Malte J. Rasch, Lorenzo Servadei (Sony AI). ID: 16
"PVT-Goal: Solving PVT-Aware Transistor Sizing Problem with Goal-Conditioned Reinforcement Learning Framework," Seunggeun Kim, David Z. Pan (The University of Texas at Austin). ID: 17
"Agentic-HLS: An Agentic Reasoning Based High-Level Synthesis System Using Large Language Models," Ali Emre Oztas, Zheyu Liu, Mahdi Jelodari (The University of Manchester). ID: 18
Anonymous. ID: 19
"An Efficient Transformer and Genetic Algorithm Based HLS Design Space Exploration," Yujie Yan, Guanhua Chen, Chang Wu (Fudan University). ID: 20
"MAGE: A Multi-Agent Engine for Automated RTL Code Generation," Yujie Zhao, Hejia Zhang, Hanxian Huang, Zhongming Yu, Jishen Zhao (University of California San Diego). ID: 21