NSF Workshop on AI for Electronic Design Automation

Plaza Ballroom at Hyatt Regency Vancouver Hotel

December 10, 2024

In the past few years, domain-specific accelerators (DSAs), such as Google's Tensor Processing Unit (TPU), have shown to offer significant performance and energy efficiency over general-purpose CPUs. However, DSAs require deep hardware knowledge to achieve high performance. Unfortunately, there are far fewer hardware designers than software developers. Leveraging AI techniques to further automate chip design becomes the key to meeting the need of rapid change in software development, which is also critical for democratizing hardware design and creating next-generation energy-efficient hardware. This workshop aims to bring researchers and practitioners from both machine learning and EDA communities to discuss how AI can address challenges in different stages of hardware design, promoting open benchmark datasets and open discussions to revolutionize chip design.

The workshop will consist of invited talks and panel discussions on a wide variety of methods and problems in this area, including but not limited to:

Attending

Important Dates

Invited Speakers and Panelists

Jeff Dean
Jeff Dean

Google

Vijay Ganesh
Vijay Ganesh

Georgia Tech

Koen Lampaert
Koen Lampaert

Broadcom

Celine Lin
Celine Lin

Georgia Tech

Yong Liu
Yong Liu

Cadence Design Systems

Pranay Prakash
Pranay Prakash

Synopsys

Subhasish Mitra
Subhasish Mitra

Stanford University

Bryan Perozzi
Bryan Perozzi

Google

Mark Ren
Mark Ren

Nvidia

Yusu Wang
Yusu Wang

UCSD

Organizers

Jason Cong
Jason Cong

UCLA

Stefanie Jegelka
Stefanie Jegelka

MIT & TU Munich

David Z. Pan
David Z. Pan

UT Austin

Yizhou Sun
Yizhou Sun

UCLA

Program Directors


Sponsors